Chipmakers proceed to claw for each spare nanometer to proceed cutting down circuits, however a know-how involving issues which might be a lot greater—a whole lot or hundreds of nanometers throughout—might be simply as vital over the subsequent 5 years.
Referred to as hybrid bonding, that know-how stacks two or extra chips atop each other in the identical bundle. That permits chipmakers to extend the variety of transistors of their processors and recollections regardless of a common slowdown within the shrinking of transistors, which as soon as drove Moore’s Legislation. On the
IEEE Digital Elements and Expertise Convention (ECTC) this previous Might in Denver, analysis teams from all over the world unveiled a wide range of hard-fought enhancements to the know-how, with just a few exhibiting outcomes that might result in a document density of connections between 3D stacked chips: some 7 million hyperlinks per sq. millimeter of silicon.
All these connections are wanted due to the brand new nature of progress in
semiconductors, Intel’s Yi Shi advised engineers at ECTC. Moore’s Legislation is now ruled by an idea referred to as system know-how co-optimization, or STCO, whereby a chip’s capabilities, reminiscent of cache reminiscence, enter/output, and logic, are fabricated individually utilizing the most effective manufacturing know-how for every. Hybrid bonding and different superior packaging tech can then be used to assemble these subsystems in order that they work each bit in addition to a single piece of silicon. However that may occur solely when there’s a excessive density of connections that may shuttle bits between the separate items of silicon with little delay or vitality consumption.
Out of all of the advanced-packaging applied sciences, hybrid bonding gives the very best density of vertical connections. Consequently, it’s the quickest rising section of the advanced-packaging business, says
Gabriella Pereira, know-how and market analyst at Yole Group. The general market is about to greater than triple to US $38 billion by 2029, based on Yole, which tasks that hybrid bonding will make up about half the market by then, though in the present day it’s only a small portion.
In hybrid bonding, copper pads are constructed on the highest face of every chip. The copper is surrounded by insulation, often silicon oxide, and the pads themselves are barely recessed from the floor of the insulation. After the oxide is chemically modified, the 2 chips are then pressed collectively face-to-face, in order that the recessed pads on every align. This sandwich is then slowly heated, inflicting the copper to broaden throughout the hole and fuse, connecting the 2 chips.
Hybrid bonding can both connect particular person chips of 1 dimension to a wafer filled with chips of a bigger dimension or bond two full wafers of chips of the identical dimension. Thanks partially to its use in digital camera chips, the latter course of is extra mature than the previous, Pereira says. For instance, engineers on the European microelectronics-research institute
Imec have created among the most dense wafer-on-wafer bonds ever, with a bond-to-bond distance (or pitch) of simply 400 nanometers. However Imec managed solely a 2-micrometer pitch for chip-on-wafer bonding.
The latter is a big enchancment over the superior 3D chips in manufacturing in the present day, which have connections about 9 μm aside. And it’s a good greater leap over the predecessor know-how: “microbumps” of solder, which have pitches within the tens of micrometers.
“With the tools out there, it’s simpler to align wafer to wafer than chip to wafer. Most processes for microelectronics are made for [full] wafers,” says
Jean-Charles Souriau, scientific chief in integration and packaging on the French analysis group CEA Leti. However it’s chip-on-wafer (or die-to-wafer) that’s making a splash in high-end processors reminiscent of these from AMD, the place the method is used to assemble compute cores and cache reminiscence in its superior CPUs and AI accelerators.
In pushing for tighter and tighter pitches for each situations, researchers are targeted on making surfaces flatter, getting certain wafers to stay collectively higher, and slicing the time and complexity of the entire course of. Getting it proper may revolutionize how chips are designed.
WoW, These Are Some Tight Pitches
The latest wafer-on-wafer (WoW) analysis that achieved the tightest pitches—from 360 nm to 500 nm—concerned lots of effort on one factor: flatness. To bond two wafers along with 100-nm-level accuracy, the entire wafer must be almost completely flat. If it’s bowed or warped to the slightest diploma, complete sections gained’t join.
Flattening wafers is the job of a course of referred to as chemical mechanical planarization, or CMP. It’s important to chipmaking usually, particularly for producing the layers of interconnects above the
transistors.
“CMP is a key parameter now we have to manage for hybrid bonding,” says Souriau. The outcomes offered at ECTC present CMP being taken to a different degree, not simply flattening throughout the wafer however decreasing mere nanometers of roundness on the insulation between the copper pads to make sure higher connections.
“It’s troublesome to say what the restrict shall be. Issues are shifting very quick.” —Jean-Charles Souriau, CEA Leti
Different researchers targeted on guaranteeing these flattened elements stick collectively strongly sufficient. They did so by experimenting with totally different floor supplies reminiscent of silicon carbonitride as a substitute of silicon oxide and through the use of totally different schemes to chemically activate the floor. Initially, when wafers or dies are pressed collectively, they’re held in place with comparatively weak hydrogen bonds, and the priority is whether or not the whole lot will keep in place throughout additional processing steps. After attachment, wafers and chips are then heated slowly, in a course of referred to as annealing, to kind stronger chemical bonds. Simply how robust these bonds are—and even the way to determine that out—was the topic of a lot of the analysis offered at ECTC.
A part of that ultimate bond energy comes from the copper connections. The annealing step expands the copper throughout the hole to kind a conductive bridge. Controlling the scale of that hole is vital, explains Samsung’s
Seung Ho Hahn. Too little enlargement, and the copper gained’t fuse. An excessive amount of, and the wafers shall be pushed aside. It’s a matter of nanometers, and Hahn reported analysis on a brand new chemical course of that he hopes to make use of to get it good by etching away the copper a single atomic layer at a time.
The standard of the connection counts, too. The metals in chip interconnects are usually not a single crystal; as a substitute they’re made up of many grains, crystals oriented in numerous instructions. Even after the copper expands, the metallic’s grain boundaries typically don’t cross from one facet to a different. Such a crossing ought to scale back a connection’s electrical resistance and enhance its reliability. Researchers at Tohoku College in Japan reported a brand new metallurgical scheme that might lastly generate giant, single grains of copper that cross the boundary. “It is a drastic change,” says
Takafumi Fukushima, an affiliate professor at Tohoku. “We are actually analyzing what underlies it.”
Different experiments mentioned at ECTC targeted on streamlining the bonding course of. A number of sought to scale back the annealing temperature wanted to kind bonds—usually round 300 °C—as to reduce any threat of injury to the chips from the extended heating. Researchers from
Utilized Supplies offered progress on a way to radically scale back the time wanted for annealing—from hours to only 5 minutes.
CoWs That Are Excellent within the Discipline
Imec used plasma etching to cube up chips and provides them chamfered corners. The method relieves mechanical stress that might intervene with bonding.Imec
Chip-on-wafer (CoW) hybrid bonding is extra helpful to makers of superior CPUs and GPUs in the meanwhile: It permits chipmakers to stack
chiplets of various sizes and to check every chip earlier than it’s certain to a different, guaranteeing that they aren’t dooming an costly CPU with a single flawed half.
However CoW comes with the entire difficulties of WoW and fewer of the choices to alleviate them. For instance, CMP is designed to flatten wafers, not particular person dies. As soon as dies have been minimize from their supply wafer and examined, there’s much less that may be performed to enhance their readiness for bonding.
However, researchers at
Intel reported CoW hybrid bonds with a 3-μm pitch, and, as talked about, a crew at Imec managed 2 μm, largely by making the transferred dies very flat whereas they have been nonetheless hooked up to the wafer and preserving them further clear all through the method. Each teams used plasma etching to cube up the dies as a substitute of the same old methodology, which makes use of a specialised blade. In contrast to a blade, plasma etching doesn’t result in chipping on the edges, which creates particles that might intervene with connections. It additionally allowed the Imec group to form the die, making chamfered corners that relieve mechanical stress that might break connections.
CoW hybrid bonding goes to be vital to the way forward for high-bandwidth reminiscence (HBM), based on a number of researchers at ECTC. HBM is a stack of DRAM dies—at present 8 to 12 dies excessive—atop a control-logic chip. Typically positioned inside the identical bundle as high-end
GPUs, HBM is essential to dealing with the tsunami of knowledge wanted to run giant language fashions like ChatGPT. Right now, HBM dies are stacked utilizing microbump know-how, so there are tiny balls of solder surrounded by an natural filler between every layer.
However with AI pushing reminiscence demand even increased, DRAM makers need to stack 20 layers or extra in HBM chips. The amount that microbumps take up implies that these stacks will quickly be too tall to suit correctly within the bundle with GPUs. Hybrid bonding would shrink the peak of HBMs and in addition make it simpler to take away extra warmth from the bundle, as a result of there can be much less thermal resistance between its layers.
“I believe it’s potential to make a more-than-20-layer stack utilizing this know-how.” —Hyeonmin Lee, Samsung
At ECTC, Samsung engineers confirmed that hybrid bonding may yield a 16-layer HBM stack. “I believe it’s potential to make a more-than-20-layer stack utilizing this know-how,” says
Hyeonmin Lee, a senior engineer at Samsung. Different new CoW know-how may additionally assist convey hybrid bonding to high-bandwidth reminiscence. Researchers at CEA Leti are exploring what’s often called self-alignment know-how, says Souriau. That may assist guarantee good CoW connections utilizing simply chemical processes. Some elements of every floor can be made hydrophobic and a few hydrophilic, leading to surfaces that will slide into place robotically.
At ECTC, researchers from Tohoku College and Yamaha Robotics reported work on an analogous scheme, utilizing the floor stress of water to align 5-μm pads on experimental DRAM chips with higher than 50-nm accuracy.
The Bounds of Hybrid Bonding
Researchers will nearly definitely hold decreasing the pitch of hybrid-bonding connections. A 200-nm WoW pitch is not only potential however fascinating,
Han-Jong Chia, a venture supervisor for pathfinding techniques at Taiwan Semiconductor Manufacturing Co. , advised engineers at ECTC. Inside two years, TSMC plans to introduce a know-how referred to as bottom energy supply. (Intel plans the identical for the top of this yr.) That’s a know-how that places the chip’s chunky power-delivery interconnects beneath the floor of the silicon as a substitute of above it. With these energy conduits out of the best way, the uppermost ranges can join higher to smaller hybrid-bonding bond pads, TSMC researchers calculate. Bottom energy supply with 200-nm bond pads would minimize down the capacitance of 3D connections a lot {that a} measure of vitality effectivity and sign pace can be as a lot as eight occasions higher than what might be achieved with 400-nm bond pads.
Chip-on-wafer hybrid bonding is extra helpful than wafer-on-wafer bonding, in that it might place dies of 1 dimension onto a wafer of bigger dies. Nonetheless, the density of connections that may be achieved is decrease than for wafer-on-wafer bonding.Imec
Sooner or later sooner or later, if bond pitches slender even additional, Chia suggests, it would turn out to be sensible to “fold” blocks of circuitry so they’re constructed throughout two wafers. That approach a few of what are actually lengthy connections inside the block may be capable to take a vertical shortcut, probably rushing computations and decreasing energy consumption.
And hybrid bonding is probably not restricted to silicon. “Right now there’s lots of improvement in silicon-to-silicon wafers, however we’re additionally seeking to do hybrid bonding between gallium nitride and silicon wafers and glass wafers…the whole lot on the whole lot,” says CEA Leti’s Souriau. His group even offered analysis on hybrid bonding for quantum-computing chips, which entails aligning and bonding superconducting niobium as a substitute of copper.
“It’s troublesome to say what the restrict shall be,” Souriau says. “Issues are shifting very quick.”
This text was up to date on 11 August 2024.
This text seems within the September 2024 print problem.
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